74_14 NOT (Schmidt Trigger).pdf

1 Data sheet acquired from Harris Semiconductor SCHS129A Features ? Unlimited Input Rise and Fall Times ? Exceptionally High Noise Immunity ? Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads ? Wide Operating Temperature Range . . . -55 o C to 125 o C ? Balanced Propagation Delay and Transition Times ? Significant Power Reduction Compared to LSTTL Logic ICs ? HC Types - 2V to 6V Operation - High Noise Immunity: N IL = 30%, N IH = 30% of V CC at V CC = 5V ? HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, V IL = 0.8V (Max), V IH = 2V (Min) - CMOS Input Compatibility, I l £ 1m A at V OL , V OH Description The ?HC14 and ?HCT14 each contain 6 inverting Schmitt Triggers in one package. Pinout CD54HC14, CD54HCT14 (CERDIP) CD74HC14, CD74HCT14 (PDIP, SOIC) TOP VIEW Ordering Information PART NUMBER TEMP. RANGE ( o C) PACKAGE CD54HC14F -55 to 125 14 Ld CERDIP CD54HC14F3A -55 to 125 14 Ld CERDIP CD74HC14E -55 to 125 14 Ld PDIP CD74HC14M -55 to 125 14 Ld SOIC CD54HCT14F -55 to 125 14 Ld CERDIP CD54HCT14F3A -55 to 125 14 Ld CERDIP CD74HCT14E -55 to 125 14 Ld PDIP CD74HCT14M -55 to 125 14 Ld SOIC NOTES: 1. When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel. 2. Die is available which meets all electrical specifications. Please contact your local TI sales office or customer service for ordering information. 1A 1Y 2A 2Y 3A 3Y GND V CC 6A 6Y 5A 5Y 4A 4Y 1 2 3 4 5 6 7 14 13 12 11 10 9 8 January 1998 - Revised May 2000 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2000, Texas Instruments Incorporated CD54/74HC14, CD54/74HCT14 High Speed CMOS Logic Hex Inverting Schmitt Trigger [ /Title (CD74H C14, CD74H CT14) /Subject (High Speed CMOS Logic Hex Invert- 2 Functional Diagram Logic Diagram TRUTH TABLE INPUT (A) OUTPUT (Y) LH HL NOTE: H= High Level L = Low Level 1A 2A 4A 5A 6A 1 3 5 9 11 13 2 4 6 8 1Y 4Y 5Y 3Y 2Y 10 12 6Y 3A GND = 7 V CC = 14 nA nY CD54/74HC14, CD54/74HCT14 3 FIGURE 1. HYSTERESIS DEFINITION, CHARACTERISTIC, AND TEST SETUP V O V H V T -V T + V I V H = V T + - V T - V CC V I GND V CC V O GND V T +V T - V H CD54/74HC14, CD54/74HCT14 4 Absolute Maximum Ratings Thermal Information DC Supply Voltage, V CC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, I IK For V I < -0.5V or V I > V CC + 0.5V . . . . . . . . . . . . . . . . . . . . . .? 20mA DC Output Diode Current, I OK For V O < -0.5V or V O > V CC + 0.5V . . . . . . . . . . . . . . . . . . . .? 20mA DC Drain Current, per Output, I O For -0.5V < V O < V CC +0.5V . . . . . . . . . . . . . . . . . . . . . . . . . .? 25mA DC Output Source or Sink Current per Output Pin, I O For V O > -0.5V or V O < V CC + 0.5V . . . . . . . . . . . . . . . . . . . .? 25mA DC V CC or Ground Current, I CC . . . . . . . . . . . . . . . . . . . . . . . . .? 50mA Operating Conditions Temperature Range, T A . . . . . . . . . . . . . . . . . . . . . . -55 o C to 125 o C Supply Voltage Range, V CC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, V I , V O . . . . . . . . . . . . . . . . . 0V to V CC Input Rise and Fall Time, t r , t f 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100ms (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100ms (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100ms (Max) Thermal Resistance (Typical, Note 3) q JA ( o C/W) q JC ( o C/W) PDIP Package . . . . . . . . . . . . . . . . . . . 90 - CERDIP Package . . . . . . . . . . . . . . . . 130 55 SOIC Package . . . . . . . . . . . . . . . . . . . 120 - Maximum Junction Temperature (Hermetic Package or Die) . . . 175 o C Maximum Junction Temperature (Plastic Package) . . . . . . . . 150 o C Maximum Storage Temperature Range . . . . . . . . . .-65 o C to 150 o C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300 o C (SOIC - Lead Tips Only) CAUTION: Stresses above those listed in ?Absolute Maximum Ratings? may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 3. q JA is measured with the component mounted on an evaluation PC board in free air. DC Electrical Specifications PARAMETER SYMBOL TEST CONDITIONS V CC (V) 25 o C -40 o C TO 85 o C -55 o C TO 125 o C UNITSV I (V) I O (mA) MIN MAX MIN MAX MIN MAX HC TYPES Input Switch Points V T + - - 2 0.7 1.5 0.7 1.5 0.7 1.5 V 4.5 1.7 3.15 1.7 3.15 1.7 3.15 V 6 2.1 4.2 2.1 4.2 2.1 4.2 V V T - - - 2 0.3 1.0 0.3 1.0 0.3 1.0 V 4.5 0.9 2.2 0.9 2.2 0.9 2.2 V 6 1.2 3.0 1.2 3.0 1.2 3.0 V V H - - 2 0.2 1.0 0.2 1.0 0.2 1.0 V 4.5 0.4 1.4 0.4 1.4 0.4 1.4 V 6 0.6 1.6 0.6 1.6 0.6 1.6 V High Level Output Voltage CMOS Loads V OH V T - or V T + -0.02 2 1.9 - 1.9 - 1.9 - V -0.02 4.5 4.4 - 4.4 - 4.4 - V -0.02 6 5.9 - 5.9 - 5.9 - V High Level Output Voltage TTL Loads --------V -4 4.5 3.98 - 3.84 - 3.7 - V -5.2 6 5.48 - 5.34 - 5.2 - V CD54/74HC14, CD54/74HCT14 5 Low Level Output Voltage CMOS Loads V OL V IH or V IL 0.02 2 - 0.1 - 0.1 - 0.1 V 0.02 4.5 - 0.1 - 0.1 - 0.1 V 0.02 6 - 0.1 - 0.1 - 0.1 V Low Level Output Voltage TTL Loads --------V 4 4.5 - 0.26 - 0.33 - 0.4 V 5.2 6 - 0.26 - 0.33 - 0.4 V Input Leakage Current I I V CC or GND -6-? 0.1 - ? 1-? 1 m A Quiescent Device Current I CC V CC or GND 06-2-20-40m A HCT TYPES Input Switch Points V T + - - 4.5 1.2 1.9 1.2 1.9 1.2 1.9 V 5.5 1.4 2.1 1.4 2.1 1.4 2.1 V V T - 4.5 0.5 1.2 0.5 1.2 0.5 1.2 V 5.5 0.6 1.4 0.6 1.4 0.6 1.4 V V H 4.5 0.4 1.4 0.4 1.4 0.4 1.4 V 5.5 0.4 1.5 0.4 1.5 0.4 1.5 V High Level Output Voltage CMOS Loads V OH V IH or V IL -0.02 4.5 4.4 - 4.4 - 4.4 - V High Level Output Voltage TTL Loads -4 4.5 3.98 - 3.84 - 3.7 - V Low Level Output Voltage CMOS Loads V OL V IH or V IL 0.02 4.5 - 0.1 - 0.1 - 0.1 V Low Level Output Voltage TTL Loads 4 4.5 - 0.26 - 0.33 - 0.4 V Input Leakage Current I I V CC and GND - 5.5 - ? 0.1 - ? 1-? 1 m A Quiescent Device Current I CC V CC or GND 0 5.5 - 2 - 20 - 40 m A Additional Quiescent Device Current Per Input Pin: 1 Unit Load D I CC (Note 4) V CC - 2.1 - 4.5 to 5.5 - 360 - 450 - 490 m A NOTE: 4. For dual-supply systems theoretical worst case (V I = 2.4V, V CC = 5.5V) specification is 1.8mA. DC Electrical Specifications (Continued) PARAMETER SYMBOL TEST CONDITIONS V CC (V) 25 o C -40 o C TO 85 o C -55 o C TO 125 o C UNITSV I (V) I O (mA) MIN MAX MIN MAX MIN MAX HCT Input Loading Table INPUT UNIT LOADS nA 0.6 NOTE: Unit Load is D I CC limit specified in DC Electrical Specifica- tions table, e.g., 360m A max at 25 o C. CD54/74HC14, CD54/74HCT14 6 Switching Specifications Input t r , t f = 6ns PARAMETER SYMBOL TEST CONDITIONS V CC (V) 25 o C -40 o C TO 85 o C -55 o C TO 125 o C UNITSMIN TYP MAX MIN MAX MIN MAX HC TYPES Propagation Delay, A to Y t PLH , t PHL C L = 50pF 2 - - 135 - 170 - 205 ns C L = 50pF 4.5 - - 27 - 34 - 41 ns C L = 15pF 5 - 11 - ----ns C L = 50pF 6 - - 23 - 29 - 35 ns Output Transition Times t TLH , t THL C L = 50pF 2 - - 75 - 95 18 110 ns 4.5 - - 15 - 19 - 22 ns 6 - - 13 - 16 - 19 ns Input Capacitance C I - - - - 10 - 10 - 10 pF Power Dissipation Capacitance (Notes 5, 6) C PD - 5-20-----pF HCT TYPES Propagation Delay, A to Y t PLH , t PHL C L = 50pF 4.5 - - 38 - 48 - 57 ns C L = 15pF 5 - 16 - ----ns Output Transition Times t TLH , t THL C L = 50pF 4.5 - - 15 - 19 - 22 ns Input Capacitance C I - - - - 10 - 10 - 10 pF Power Dissipation Capacitance (Notes 5, 6) C PD - 5-20-----pF NOTES: 5. C PD is used to determine the dynamic power consumption, per inverter. 6. P D = V CC 2 f i (C PD + C L ) where f i = input frequency, C L = output load capacitance, V CC = supply voltage. Test Circuits and Waveforms FIGURE 2. HC TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC FIGURE 3. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC t PHL t PLH t THL t TLH 90% 50% 10% 50% 10% INVERTING OUTPUT INPUT GND V CC t r = 6ns t f = 6ns 90% t PHL t PLH t THL t TLH 2.7V 1.3V 0.3V 1.3V 10% INVERTING OUTPUT INPUT GND 3V t r = 6ns t f = 6ns 90% CD54/74HC14, CD54/74HCT14 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI?s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer?s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI?s publication of information regarding any third party?s products or services does not constitute TI?s approval, warranty or endorsement thereof. Copyright ? 2000, Texas Instruments Incorporated Texas Instruments, Incorporated "High-Speed CMOS Logic Hex Inverting Schmitt Trigger" schs129a,schs129 Data Sheet