ECE445lecture11.ppt

ECE 445 ? Computer Organization Multi-cycle Processor (Lecture #11) ECE 445 - Computer Organization * Comparison Multi-cycle Single-cycle Each step takes one clock cycle Each instruction takes one clock cycle Re-use functional units more than once per instruction Dedicated functional units (only used once per instruction) One adder (in the ALU) Multiple adders Different number of clock cycles per instruction One clock cycle per instruction (for all instructions) Single memory unit for instructions and data Two memory units, one for instructions and one for data More complex control (State Machine) Simple control (Boolean Logic) ECE 445 - Computer Organization ECE 445 - Computer Organization * A multi-cycle processor is realized through the addition of registers after each of the major functional units (to hold the values between the steps of the instruction) ECE 445 - Computer Organization ECE 445 - Computer Organization * Fig. 5.26 (p. 320) with proper annotation data address instruction address Looks like output of Data Memory Looks like output of Instruction Memory Muxes select which inputs ALU will operate on ECE 445 - Computer Organization ECE 445 - Computer Organization * Fig. 5.28 (p. 323) ECE 445 - Computer Organization ECE 445 - Computer Organization * Instruction Execution Steps ECE 445 - Computer Organization ECE 445 - Computer Organization * Instruction Execution Steps Instruction Fetch Instruction Decode and Register Fetch Execution, Memory address computation, or Branch completion Memory access or R-type instruction completion Memory read completion ECE 445 - Computer Organization ECE 445 - Computer Organization * 1. Instruction Fetch The instruction is loaded from memory into the Instruction Register (IR); the address of the instruction is stored in the Program Counter (PC). IR = M[PC] The Program Counter (PC) is incremented by 4. PC = PC + 4 The PC is updated on the next rising clock edge. ECE 445 - Computer Organization * 2. Instruction Decode and Register Fetch Load register A with contents of Register File register specified in bits 25..21 of instruction. A = R[ IR[ 25:21 ] ] Load register B with contents of Register File register specified in bits 20..16 of instruction. B = R[ IR[ 20:16 ] ] Compute the Branch Target Address using ALU and immediate value specified in instruction. ALUOut = PC + ( SignExt( IR[ 15:0 ] ) << 2 ) Reading register is not harmful even if it is unnecessary Reading register is not harmful even if it is unnecessary Calculating the branch target address is not harmful if the instruction is not a branch ECE 445 - Computer Organization * 3. Execution, Memory Address Computation, or Branch Completion This is the first cycle during which the datapath operation is determined by the instruction class. ALU Operations (R-type) Memory Reference Branch Jump ECE 445 - Computer Organization ECE 445 - Computer Organization * (a) ALU Operations The ALU implements the operation specified by the opcode and function code (in the instruction). ALUOut = R[A] op R[B] The ALU operation to be implemented. Example: add, sub, and, or, ... ECE 445 - Computer Organization ECE 445 - Computer Organization * (b) Memory Reference The ALU calculates the memory address. ALUOut = R[A] + SignExt( IR[15:0] ) Base address offset Example: sw $s1, -4($s2) ECE 445 - Computer Organization ECE 445 - Computer Organization * (c) Branch The ALU is used to compare the contents of the two registers specified in the branch instruction. The Zero signal is used to determine whether the branch should be taken. PC = ALUOut if ( R[A] == R[B] ) Sets the PC to the Branch Target address if condition is true. Overwrites PC = PC + 4 from instruction fetch if branch is taken. ECE 445 - Computer Organization ECE 445 - Computer Organization * (d) Jump The PC is replaced by the Jump Address. PC = PC[31:28] || IR[25:0] || 00 Upper 4 bits of current PC 26-bit address specified in instruction Concatenates the upper 4 bits from the PC, the 26-bit address, and ?00? to form the new value of the PC. concatenate ECE 445 - Computer Organization ECE 445 - Computer Organization * 4. Memory Access or R-type Instruction Completion The instruction class, again, determines which datapath operation is implemented during this cycle. ALU Operations (R-type) Memory Reference ECE 445 - Computer Organization ECE 445 - Computer Organization * (a) ALU Operations The result of an ALU operation is stored in the register specified in the instruction. R[ IR[ 15:11 ] ] = ALUOut Register specified in instruction Result of ALU operation ECE 445 - Computer Organization ECE 445 - Computer Organization * (b) Memory Reference If the instruction is a Load, a data word is retrieved from memory. R[MDR] = M[ ALUOut ] If the instruction is a Store, a data word is written to memory. M[ ALUOut ] = R[B] Memory Data Register ECE 445 - Computer Organization ECE 445 - Computer Organization * 5. Memory Read Completion During this step, the Load operations complete by writing back the value from memory into the register specified in the instruction. R[ IR[ 20:16 ] ] = MDR Memory Data Register Register specified in instruction ECE 445 - Computer Organization ECE 445 - Computer Organization * Summary of Instruction Execution Steps Instruction Class 1 2 3 4 5 Clock Cycles ALU (R-type) x x x x 4 Load x x x x x 5 Store x x x x 4 Branch x x x 3 Jump x x x 3 ECE 445 - Computer Organization ECE 445 - Computer Organization * The Control Unit ECE 445 - Computer Organization ECE 445 - Computer Organization * Requires a relatively simple control unit. The necessary combinational logic can be designed from a Truth Table. Single-cycle Machine ECE 445 - Computer Organization ECE 445 - Computer Organization * Multi-cycle Machine Requires a more complex control unit than the Single-cycle Machine. Can be implemented either as a State Machine or using Microcode. hardware microprogramming ECE 445 - Computer Organization ECE 445 - Computer Organization * Fig. 5.37 (p. 338) FSM for the Control Unit ECE 445 - Computer Organization