HW7.pdf

ECE 331 ? Digital System Design Homework #7 In this homework assignment you will demonstrate your knowledge of Logic Circuit Design, Multi-bit Adder circuits, and Two's Complement Addition / Subtraction circuits. Logic Circuit Design For the following logic circuit design problems, implement the four-step design process: Step #1: Define the inputs and outputs. Step #2: Construct the Truth Table Step #3: Using a K-map, derive the minimum SOP and POS Boolean expressions. Step #4: Draw the logic circuit diagram using only AND, OR, and NOT gates for the expression that requires the fewest number of gates. (Do not count NOT gates when determining the gate count for each expression). 1. Given a Binary Coded Decimal (BCD) number, b3b2b1b0 (where b0 is the LSB), design a combinational logic circuit that outputs a logic 1 iff the BCD number is odd. Assume that the unused input combinations never occur. 2. Given two 2-bit unsigned binary numbers, A (a1a0) and B (b1b0), design a combinational logic circuit that produces the 2-bit sum and carry-out (s1s0, cout). Use multiple-input gates where possible. Use AND, OR, NOT, and XOR gates. Multi-bit Adder Circuits 3. Draw the logic circuit diagram for a 2-bit Ripple Carry Adder in terms of AND, OR, NOT, and XOR gates. Use multiple-input gates where possible. (a) Using the table on the next page, determine the gate count for this 2-bit adder circuit. (b) Determine the worst-case propagation delay for this 2-bit adder circuit in terms of number of gates (i.e. number of gates between the input and output for the longest delay path). Do not count NOT gates. 4. Draw the logic circuit diagram for a 2-bit Carry Lookahead Adder in terms of AND, OR, NOT, and XOR gates. Use multiple-input gates where possible. (a) Using the table on the next page, determine the gate count for this 2-bit adder circuit. (b) Determine the worst-case propagation delay for this 2-bit adder circuit in terms of number of gates (i.e. number of gates between the input and output for the longest delay path). Do not count NOT gates. Page 1 of 3 ECE 331 ? Digital System Design 5. Referring to the logic circuit diagram drawn in problem #2 above: (a) Using the table below, determine the gate count for this 2-bit adder circuit. (b) Determine the worst-case propagation delay for this 2-bit adder circuit in terms of number of gates (i.e. number of gates between the input and output for the longest delay path). Do not count NOT gates. Gate Equivalent Gate Count Gate Equivalent Gate Count 2-input AND 1.5 Inverter (NOT) 0.5 3-input AND 2 2-input NAND 1 2-input OR 1.5 3-input NAND 1.5 3-input OR 2 2-input NOR 1 2-input XOR 3 3-input NOR 1.5 3-input XOR 5.5 Page 2 of 3 ECE 331 ? Digital System Design Two's Complement Adder / Subtractor Circuit 6. Consider the Adder / Subtractor circuit given below. (a) Given the values for the inputs S (the Add/Sub' input), A (A3A2A1A0), and B (B3B2B1B0), in the table below, determine the sum (S3S2S1S0) and carry-out (C4) for each case. S (Add/Sub') A3A2A1A0 B3B2B1B0 S3 S2 S1 S0 C4 0 1 0 1 1 0 1 1 1 1 1 0 0 1 0 0 1 1 1 0 1 0 1 0 1 1 1 0 0 1 1 0 1 1 0 0 (b) Design the logic required to detect overflow in this adder/subtractor circuit. In class we discussed the logic circuit required to detect overflow in a 4-bit adder. Be sure to consider the fact that this circuit implements subtraction as well as addition. Page 3 of 3 Owner HW7