Name: G Number: Laboratory #10 ECE 332 1 Introduction In this laboratory you will design a 4-bit parallel input/parallel output shift left register and im- plement it on the Cool Runner-2 CPLD board. Parts of this have already been completed in the pre-lab. ? Designing a 4-bit shift left register and drawing its circuit diagram(pre-lab, Part 2) ? Hint: Your circuit diagram should contain D Flip-Flops and 2x1 Multiplexers. As a part of this lab you must complete ? Write the VHDL code which implements the 4-bit shift left register. ? Implement your code on the Cool runner 2 CPLD board. 2 Circuit to be implemented as a part of Lab-10 Re-iterating from pre-lab: Design a 4-bit parallel input/ parallel output Shift Register with the following charecterstics: ? A mode control signal ?Select? ? When Select = ?0?, the register loads Di. ? When Select = ?1?, the register shifts left (and Q0 receives Serial input). ? A rising-edge triggred clock, Clock. ? A serial input to the register, ?Serial Input?. 3 Submissions for Lab-10 Attach the following waveforms ? Post-Fit waveform. 1 ECE 332 Lab 10 2 4?bit Shift RegisterSerial Input Select Clock Q1 Q0Q2Q3 D3 D2 D1 D0 Report Following Parameters: ? Cell Usage from Synthesis Report. ? VHDL code for entire circuit including your new package/components (you don?t need to submit the package file already provided to you) ? Resource Summary From Fitter report. You have to write the UCF file. 4 Bonus Lab Design a 4-bit parallel input/parallel output shift Left and Right register and implement it on the Cool runner 2 CPLD board. 4.1 Specifications for the Bonus lab part Port Name Port Type Function D(3 downto 0) Input Parallel Input to the Shift Register Select Input This input selects whether to load data or shift data in the register Select-l-r Input This input selects whether to shift left or right. Serial Input Input Provides serial input to the register Clock Input Provides clock to the shift register Q(3 downto 0) Output Parallel output from the shift register Best of Luck!! D:/332_lab/332_lab_10/lab_10.dvi
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