Name: G Number: Laboratory #BCD-to-7 Segment Decoder ECE 332 1 Introduction In this laboratory you will design and simulate a 4 bit BCD to 7 Segment decoder and simulate its functionality on the Cool Runner-2 CPLD board. Parts of this you have already completed in the pre-lab. 2 Design and Simulate a 4 bit BCD to 7 Segment Decoder In the pre-lab you designed a 4 bit BCD to 7 Segment Decoder. In lab you will complete this design and simulate its functionality. You will be expected to complete the following items as part of this experiment: 1. Completed Truth Table (pre-lab) 2. Completed Karnaugh Maps (pre-lab) 3. Simplified logic equations (pre-lab) 4. Completed Circuit Diagram (pre-lab) 5. Simulate and Program the CPLD using the VHDL you described 6. Attach the necessary files and the Report the implementation parameters described in the next section 2.1 Circuit Diagram implementation in VHDL Write the VHDL code to implement the Logic equations for outputs a, b, c, d, e, f and g. You can use either behavioral coding or structural coding. Save and attach the following waveforms in your lab report: ? Functional or Behavorial Simulation waveform ? Post-Fit waveform. Report Following Parameters: ? Cell Usage from Synthesis Report. ? Print out the RTL Schematic view. ? Resource Summary From Fitter report. 1 ECE 332 Lab #5 2 3 Implementing the circuit on the CPLD board You will use the input circuit that you built in Lab 3 to provide the BCD inputs (i.e. D3, D2, D1, and D0). You will need to write the UCF file for this experiment. If you need help writing the UCF file, please consult the documents provided in the Documentation Folder on your ?CoolRunner-2 CPLD Starter Kit Resource CD?. Best of Luck!! C:/Documents and Settings/raj velegalati/Desktop/332_labs/binary_adders/lab_5.dvi
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