Name: G Number: Laboratory #Binary Adder Circuits ECE 332 1 Introduction In this laboratory you will design and simulate a Half Adder, Full Adder using TTL gates and simulate the functionality of Half and Full adders and a 4-bit ripple carry adder on the Cool Runner-2 CPLD board. Parts of this have already been completed in the pre-lab. 2 Design and Simulate a Half and Full Adder In the pre-lab you designed a Half and Full adder. In lab you will complete this design and simulate its functionality using TTL gates. You will be expected to complete the following items as part of this experiment: 1. Completed Truth Table, derive the equations for Half adder (pre-lab) 2. Draw the circuit diagram for a Half Adder (pre-lab) 3. Draw the circuit diagram for a Full Adder implemented using two half adder (pre-lab) 4. Read up and draw the circuit diagram for a 4-bit Ripple carry adders using full adders (pre- lab) 5. Implement Half Adder using TTL gate 6. Implement Full Adder using two half adders using TTL gate 7. Write the VHDL code for a Half, Full and a 4-bit Ripple carry adder and implement it on the CPLD board 3 Implement Half Adder and Full Adder using TTL gates As a part of your lab report Draw the pin diagrams for both Half and Full adders. Verify the functionality 1 ECE 332 Lab: Adders 2 4 Implementing the circuit on the CPLD board Write the VHDL code to implement the Half, Full and Ripple carry adders. You can use behavioral style of VHDL coding to describe Half and Full adders. You must use structral type of VHDL coding to describe a 4-bit ripple carry adder. Attach the following waveforms Functional or Behavorial Simulation waveform Post-Fit waveform. Report Following Parameters: Cell Usage from Synthesis Report for Half, Full and 4-bit Ripple carry adders. Print out the RTL Schematic view for Full and a 4-bit Ripple carry adder. Resource Summary From Fitter report for Full and 4-bit Ripple carry adder. You have to write the UCF le. 5 Bonus Part Answer the folloing question: You are asked to code a generic i.e. a n-bit Ripple carry adder. Write down the changes you are going to make in your VHDL code written for a 4-bit Ripple carry adder initially. Write the VHDL code for the generic ripple carry adder and show it to the instructor. Ask your lab instructors what does the term ?Latency? mean or better yet nd out yourself!!! What is Latency?. What is its units? What is the Latency for the 4-bit Ripple carry adder that you have coded as a part of your lab. Best of Luck!!
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