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- StudyBlue
- Virginia
- George Mason University
- Electrical Engineering
- Electrical Engineering 331
- Dr. Craig Lorie
- Lecture_21.ppt

Shafa A.

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ECE 331 – Digital System Design Finite State Machines (Lecture #21) State Assignment Problem State Assignment Problem Some state assignments are better than others. The state assignment influences the complexity of the state machine. The combinational logic required in the state machine design is dependent on the state assignment. Types of state assignment Binary encoding: 2N states → N Flip-Flops Gray-code encoding: 2N states → N Flip-Flops One-hot encoding: N states → N Flip-Flops Revisiting an earlier example: Design a sequential logic circuit that meets the following specifications: 1. The circuit has one input, w, and one output, z. 2. All changes in the circuit occur on the positive edge of the clock. 3. The output z is equal to 1 if during the two immediately preceding clock cycles the input w was equal to 1. Otherwise, the value of z is equal to 0. A circuit that detects the occurrence of a particular pattern on its input is referred to as a sequence detector. Example: State Diagram C z = 1 Reset B z 0 = A z 0 = w 0 = w 1 = w 1 = w 0 = w 0 = w 1 = Example: State Table Present Next state Output state w = 0 w = 1 z A A B 0 B A C 0 C A C 1 Example: State Assignment #1 Present Next state state w = 0 w = 1 Output y 2 y 1 Y 2 Y 1 Y 2 Y 1 z A 00 00 01 0 B 01 00 10 0 C 10 00 10 1 11 dd dd d Binary encoding Example: Implementation Y2 = w.(y2 + y1) Y1 = w.y2'.y1' z = y2 Example: State Assignment #2 2-bit Gray-code encoding Present Next state state w = 0 w = 1 Output y 2 y 1 Y 2 Y 1 Y 2 Y 1 z A 00 00 01 0 B 01 00 11 0 C 11 00 11 1 10 dd dd d Example: Implementation D Q Q D Q Q Y 2 Y 1 w Clock z y 1 y 2 Resetn Y2 = w.y1 Y1 = w z = y2 Example: State Assignment #3 One-hot encoding Present Next state state w = 0 w = 1 Output y 3 y 2 y 1 Y 3 Y 2 Y 1 Y 3 Y 2 Y 1 z A 001 001 010 0 B 010 001 100 0 C 100 001 100 1 Only one flip-flop is set to 1 for each state. The remaining combination of state variables are not used. Example: Implementation Resetn Y2 = w.y1 Y1 = w ' z = y3 Y3 = w.y1' D Q Q D Q Q Y 2 Y 1 w Clock y 1 y 2 D Q Q Y 3 z y 3 State Minimization Definition: Two states Si and Sj are said to be equivalent if and only if for every possible input sequence, the same output sequence will be produced regardless of whether Si or Sj is the initial state. Definition: A partition consists of one or more blocks, where each block comprises a subset of states that may be equivalent, but the states in a given block are definitely not equivalent to the states in other blocks. State Minimization: Partitioning State Minimization through Partitioning: Form an initial partition (P1) that includes all states. Form a second partition (P2) by separating the states into two blocks based upon their output values. Form a third partition (P3) by separating the states into blocks corresponding to the next state values. Continue partitioning until two successive partitions are the same (i.e. PN-1 = PN). All states in any one block are equivalent. Equivalent states can be combined into a single state. Example: Use partitioning to minimize the number of states in the following Finite State Machine (FSM). Example: State Diagram Example: State Table Present Next state Output state w = 0 w = 1 z A B C 1 B D F 1 C F E 0 D B G 1 E F C 0 F E D 0 G F G 0 Example: Partition P1 Initial Partition: P1 = (ABCDEFG) The initial partition contains all states in the state diagram / table. Example: Partition P2 Present Next state Output state w = 0 w = 1 z A B C 1 B D F 1 C F E 0 D B G 1 E F C 0 F E D 0 G F G 0 Separate states based on output value. P2 = (ABD)(CEFG) Example: Partition P3 Separate states based on next state values. P3 = (ABD)(CEG)(F) ABD CEFG BDB CFG FFEF ECDG 0 1 0 1 Example: Partition P4 Separate states based on next state values. P4 = (AD)(CEG)(F)(B) ABD CEG BDB CFG FFF ECG 0 1 0 1 Example: Partition P5 Separate states based on next state values. P5 = (AD)(CEG)(F)(B) AD CEG BB CG FFF ECG 0 1 0 1 Example: Partitioning Complete Since P4 = P5, state minimization is complete. The equivalent states are: A = D C = E = G B F Thus, the FSM can be realized with just 4 states. Example: Minimized State Table Present Nextstate Output state w = 0 w = 1 z A B C 1 B A F 1 C F C 0 F C A 0 Example: Minimized State Diagram Acknowledgments The slides used in this lecture were taken, with permission, from those provided by McGraw-Hill for Fundamentals of Digital Logic with VHDL Design (3rd Edition). They are the property of and are copyrighted by McGraw-Hill Higher Education.

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